1 /*
2 * Copyright (C) 2017 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <stdint.h>
18
19 #include <gtest/gtest.h>
20
21 #include <unwindstack/Elf.h>
22 #include <unwindstack/ElfInterface.h>
23 #include <unwindstack/MapInfo.h>
24 #include <unwindstack/RegsArm.h>
25 #include <unwindstack/RegsArm64.h>
26 #include <unwindstack/RegsX86.h>
27 #include <unwindstack/RegsX86_64.h>
28 #include <unwindstack/RegsMips.h>
29 #include <unwindstack/RegsMips64.h>
30
31 #include "ElfFake.h"
32 #include "MemoryFake.h"
33 #include "RegsFake.h"
34
35 namespace unwindstack {
36
37 class RegsTest : public ::testing::Test {
38 protected:
SetUp()39 void SetUp() override {
40 memory_ = new MemoryFake;
41 elf_.reset(new ElfFake(memory_));
42 elf_interface_ = new ElfInterfaceFake(elf_->memory());
43 elf_->FakeSetInterface(elf_interface_);
44 }
45
46 ElfInterfaceFake* elf_interface_;
47 MemoryFake* memory_;
48 std::unique_ptr<ElfFake> elf_;
49 };
50
TEST_F(RegsTest,regs32)51 TEST_F(RegsTest, regs32) {
52 RegsImplFake<uint32_t> regs32(50);
53 ASSERT_EQ(50U, regs32.total_regs());
54
55 uint32_t* raw = reinterpret_cast<uint32_t*>(regs32.RawData());
56 for (size_t i = 0; i < 50; i++) {
57 raw[i] = 0xf0000000 + i;
58 }
59 regs32.set_pc(0xf0120340);
60 regs32.set_sp(0xa0ab0cd0);
61
62 for (size_t i = 0; i < 50; i++) {
63 ASSERT_EQ(0xf0000000U + i, regs32[i]) << "Failed comparing register " << i;
64 }
65
66 ASSERT_EQ(0xf0120340U, regs32.pc());
67 ASSERT_EQ(0xa0ab0cd0U, regs32.sp());
68
69 regs32[32] = 10;
70 ASSERT_EQ(10U, regs32[32]);
71 }
72
TEST_F(RegsTest,regs64)73 TEST_F(RegsTest, regs64) {
74 RegsImplFake<uint64_t> regs64(30);
75 ASSERT_EQ(30U, regs64.total_regs());
76
77 uint64_t* raw = reinterpret_cast<uint64_t*>(regs64.RawData());
78 for (size_t i = 0; i < 30; i++) {
79 raw[i] = 0xf123456780000000UL + i;
80 }
81 regs64.set_pc(0xf123456780102030UL);
82 regs64.set_sp(0xa123456780a0b0c0UL);
83
84 for (size_t i = 0; i < 30; i++) {
85 ASSERT_EQ(0xf123456780000000U + i, regs64[i]) << "Failed reading register " << i;
86 }
87
88 ASSERT_EQ(0xf123456780102030UL, regs64.pc());
89 ASSERT_EQ(0xa123456780a0b0c0UL, regs64.sp());
90
91 regs64[8] = 10;
92 ASSERT_EQ(10U, regs64[8]);
93 }
94
TEST_F(RegsTest,rel_pc)95 TEST_F(RegsTest, rel_pc) {
96 EXPECT_EQ(4U, GetPcAdjustment(0x10, elf_.get(), ARCH_ARM64));
97 EXPECT_EQ(4U, GetPcAdjustment(0x4, elf_.get(), ARCH_ARM64));
98 EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_ARM64));
99 EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM64));
100 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM64));
101 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_ARM64));
102
103 EXPECT_EQ(1U, GetPcAdjustment(0x100, elf_.get(), ARCH_X86));
104 EXPECT_EQ(1U, GetPcAdjustment(0x2, elf_.get(), ARCH_X86));
105 EXPECT_EQ(1U, GetPcAdjustment(0x1, elf_.get(), ARCH_X86));
106 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_X86));
107
108 EXPECT_EQ(1U, GetPcAdjustment(0x100, elf_.get(), ARCH_X86_64));
109 EXPECT_EQ(1U, GetPcAdjustment(0x2, elf_.get(), ARCH_X86_64));
110 EXPECT_EQ(1U, GetPcAdjustment(0x1, elf_.get(), ARCH_X86_64));
111 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_X86_64));
112
113 EXPECT_EQ(8U, GetPcAdjustment(0x10, elf_.get(), ARCH_MIPS));
114 EXPECT_EQ(8U, GetPcAdjustment(0x8, elf_.get(), ARCH_MIPS));
115 EXPECT_EQ(0U, GetPcAdjustment(0x7, elf_.get(), ARCH_MIPS));
116 EXPECT_EQ(0U, GetPcAdjustment(0x6, elf_.get(), ARCH_MIPS));
117 EXPECT_EQ(0U, GetPcAdjustment(0x5, elf_.get(), ARCH_MIPS));
118 EXPECT_EQ(0U, GetPcAdjustment(0x4, elf_.get(), ARCH_MIPS));
119 EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_MIPS));
120 EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_MIPS));
121 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_MIPS));
122 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_MIPS));
123
124 EXPECT_EQ(8U, GetPcAdjustment(0x10, elf_.get(), ARCH_MIPS64));
125 EXPECT_EQ(8U, GetPcAdjustment(0x8, elf_.get(), ARCH_MIPS64));
126 EXPECT_EQ(0U, GetPcAdjustment(0x7, elf_.get(), ARCH_MIPS64));
127 EXPECT_EQ(0U, GetPcAdjustment(0x6, elf_.get(), ARCH_MIPS64));
128 EXPECT_EQ(0U, GetPcAdjustment(0x5, elf_.get(), ARCH_MIPS64));
129 EXPECT_EQ(0U, GetPcAdjustment(0x4, elf_.get(), ARCH_MIPS64));
130 EXPECT_EQ(0U, GetPcAdjustment(0x3, elf_.get(), ARCH_MIPS64));
131 EXPECT_EQ(0U, GetPcAdjustment(0x2, elf_.get(), ARCH_MIPS64));
132 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_MIPS64));
133 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_MIPS64));
134 }
135
TEST_F(RegsTest,rel_pc_arm)136 TEST_F(RegsTest, rel_pc_arm) {
137 // Check fence posts.
138 elf_->FakeSetLoadBias(0);
139 EXPECT_EQ(2U, GetPcAdjustment(0x5, elf_.get(), ARCH_ARM));
140 EXPECT_EQ(2U, GetPcAdjustment(0x4, elf_.get(), ARCH_ARM));
141 EXPECT_EQ(2U, GetPcAdjustment(0x3, elf_.get(), ARCH_ARM));
142 EXPECT_EQ(2U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM));
143 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM));
144 EXPECT_EQ(0U, GetPcAdjustment(0x0, elf_.get(), ARCH_ARM));
145
146 elf_->FakeSetLoadBias(0x100);
147 EXPECT_EQ(0U, GetPcAdjustment(0x1, elf_.get(), ARCH_ARM));
148 EXPECT_EQ(2U, GetPcAdjustment(0x2, elf_.get(), ARCH_ARM));
149 EXPECT_EQ(2U, GetPcAdjustment(0xff, elf_.get(), ARCH_ARM));
150 EXPECT_EQ(2U, GetPcAdjustment(0x105, elf_.get(), ARCH_ARM));
151 EXPECT_EQ(2U, GetPcAdjustment(0x104, elf_.get(), ARCH_ARM));
152 EXPECT_EQ(2U, GetPcAdjustment(0x103, elf_.get(), ARCH_ARM));
153 EXPECT_EQ(2U, GetPcAdjustment(0x102, elf_.get(), ARCH_ARM));
154 EXPECT_EQ(0U, GetPcAdjustment(0x101, elf_.get(), ARCH_ARM));
155 EXPECT_EQ(0U, GetPcAdjustment(0x100, elf_.get(), ARCH_ARM));
156
157 // Check thumb instructions handling.
158 elf_->FakeSetLoadBias(0);
159 memory_->SetData32(0x2000, 0);
160 EXPECT_EQ(2U, GetPcAdjustment(0x2005, elf_.get(), ARCH_ARM));
161 memory_->SetData32(0x2000, 0xe000f000);
162 EXPECT_EQ(4U, GetPcAdjustment(0x2005, elf_.get(), ARCH_ARM));
163
164 elf_->FakeSetLoadBias(0x400);
165 memory_->SetData32(0x2100, 0);
166 EXPECT_EQ(2U, GetPcAdjustment(0x2505, elf_.get(), ARCH_ARM));
167 memory_->SetData32(0x2100, 0xf111f111);
168 EXPECT_EQ(4U, GetPcAdjustment(0x2505, elf_.get(), ARCH_ARM));
169 }
170
TEST_F(RegsTest,elf_invalid)171 TEST_F(RegsTest, elf_invalid) {
172 MapInfo map_info(nullptr, nullptr, 0x1000, 0x2000, 0, 0, "");
173 Elf* invalid_elf = new Elf(nullptr);
174 map_info.set_elf(invalid_elf);
175
176 EXPECT_EQ(0x500U, invalid_elf->GetRelPc(0x1500, &map_info));
177 EXPECT_EQ(2U, GetPcAdjustment(0x500U, invalid_elf, ARCH_ARM));
178 EXPECT_EQ(2U, GetPcAdjustment(0x511U, invalid_elf, ARCH_ARM));
179
180 EXPECT_EQ(0x600U, invalid_elf->GetRelPc(0x1600, &map_info));
181 EXPECT_EQ(4U, GetPcAdjustment(0x600U, invalid_elf, ARCH_ARM64));
182
183 EXPECT_EQ(0x700U, invalid_elf->GetRelPc(0x1700, &map_info));
184 EXPECT_EQ(1U, GetPcAdjustment(0x700U, invalid_elf, ARCH_X86));
185
186 EXPECT_EQ(0x800U, invalid_elf->GetRelPc(0x1800, &map_info));
187 EXPECT_EQ(1U, GetPcAdjustment(0x800U, invalid_elf, ARCH_X86_64));
188
189 EXPECT_EQ(0x900U, invalid_elf->GetRelPc(0x1900, &map_info));
190 EXPECT_EQ(8U, GetPcAdjustment(0x900U, invalid_elf, ARCH_MIPS));
191
192 EXPECT_EQ(0xa00U, invalid_elf->GetRelPc(0x1a00, &map_info));
193 EXPECT_EQ(8U, GetPcAdjustment(0xa00U, invalid_elf, ARCH_MIPS64));
194 }
195
TEST_F(RegsTest,arm_verify_sp_pc)196 TEST_F(RegsTest, arm_verify_sp_pc) {
197 RegsArm arm;
198 uint32_t* regs = reinterpret_cast<uint32_t*>(arm.RawData());
199 regs[13] = 0x100;
200 regs[15] = 0x200;
201 EXPECT_EQ(0x100U, arm.sp());
202 EXPECT_EQ(0x200U, arm.pc());
203 }
204
TEST_F(RegsTest,arm64_verify_sp_pc)205 TEST_F(RegsTest, arm64_verify_sp_pc) {
206 RegsArm64 arm64;
207 uint64_t* regs = reinterpret_cast<uint64_t*>(arm64.RawData());
208 regs[31] = 0xb100000000ULL;
209 regs[32] = 0xc200000000ULL;
210 EXPECT_EQ(0xb100000000U, arm64.sp());
211 EXPECT_EQ(0xc200000000U, arm64.pc());
212 }
213
TEST_F(RegsTest,x86_verify_sp_pc)214 TEST_F(RegsTest, x86_verify_sp_pc) {
215 RegsX86 x86;
216 uint32_t* regs = reinterpret_cast<uint32_t*>(x86.RawData());
217 regs[4] = 0x23450000;
218 regs[8] = 0xabcd0000;
219 EXPECT_EQ(0x23450000U, x86.sp());
220 EXPECT_EQ(0xabcd0000U, x86.pc());
221 }
222
TEST_F(RegsTest,x86_64_verify_sp_pc)223 TEST_F(RegsTest, x86_64_verify_sp_pc) {
224 RegsX86_64 x86_64;
225 uint64_t* regs = reinterpret_cast<uint64_t*>(x86_64.RawData());
226 regs[7] = 0x1200000000ULL;
227 regs[16] = 0x4900000000ULL;
228 EXPECT_EQ(0x1200000000U, x86_64.sp());
229 EXPECT_EQ(0x4900000000U, x86_64.pc());
230 }
231
TEST_F(RegsTest,mips_verify_sp_pc)232 TEST_F(RegsTest, mips_verify_sp_pc) {
233 RegsMips mips;
234 uint32_t* regs = reinterpret_cast<uint32_t*>(mips.RawData());
235 regs[29] = 0x100;
236 regs[32] = 0x200;
237 EXPECT_EQ(0x100U, mips.sp());
238 EXPECT_EQ(0x200U, mips.pc());
239 }
240
TEST_F(RegsTest,mips64_verify_sp_pc)241 TEST_F(RegsTest, mips64_verify_sp_pc) {
242 RegsMips64 mips64;
243 uint64_t* regs = reinterpret_cast<uint64_t*>(mips64.RawData());
244 regs[29] = 0xb100000000ULL;
245 regs[32] = 0xc200000000ULL;
246 EXPECT_EQ(0xb100000000U, mips64.sp());
247 EXPECT_EQ(0xc200000000U, mips64.pc());
248 }
249
TEST_F(RegsTest,arm64_strip_pac_mask)250 TEST_F(RegsTest, arm64_strip_pac_mask) {
251 RegsArm64 arm64;
252 arm64.SetPseudoRegister(Arm64Reg::ARM64_PREG_RA_SIGN_STATE, 1);
253 arm64.SetPACMask(0x007fff8000000000ULL);
254 arm64.set_pc(0x0020007214bb3a04ULL);
255 EXPECT_EQ(0x0000007214bb3a04ULL, arm64.pc());
256 }
257
TEST_F(RegsTest,arm64_fallback_pc)258 TEST_F(RegsTest, arm64_fallback_pc) {
259 RegsArm64 arm64;
260 arm64.SetPACMask(0x007fff8000000000ULL);
261 arm64.set_pc(0x0020007214bb3a04ULL);
262 arm64.fallback_pc();
263 EXPECT_EQ(0x0000007214bb3a04ULL, arm64.pc());
264 }
265
TEST_F(RegsTest,machine_type)266 TEST_F(RegsTest, machine_type) {
267 RegsArm arm_regs;
268 EXPECT_EQ(ARCH_ARM, arm_regs.Arch());
269
270 RegsArm64 arm64_regs;
271 EXPECT_EQ(ARCH_ARM64, arm64_regs.Arch());
272
273 RegsX86 x86_regs;
274 EXPECT_EQ(ARCH_X86, x86_regs.Arch());
275
276 RegsX86_64 x86_64_regs;
277 EXPECT_EQ(ARCH_X86_64, x86_64_regs.Arch());
278
279 RegsMips mips_regs;
280 EXPECT_EQ(ARCH_MIPS, mips_regs.Arch());
281
282 RegsMips64 mips64_regs;
283 EXPECT_EQ(ARCH_MIPS64, mips64_regs.Arch());
284 }
285
286 template <typename RegisterType>
clone_test(Regs * regs)287 void clone_test(Regs* regs) {
288 RegisterType* register_values = reinterpret_cast<RegisterType*>(regs->RawData());
289 int num_regs = regs->total_regs();
290 for (int i = 0; i < num_regs; ++i) {
291 register_values[i] = i;
292 }
293
294 std::unique_ptr<Regs> clone(regs->Clone());
295 ASSERT_EQ(regs->total_regs(), clone->total_regs());
296 RegisterType* clone_values = reinterpret_cast<RegisterType*>(clone->RawData());
297 for (int i = 0; i < num_regs; ++i) {
298 EXPECT_EQ(register_values[i], clone_values[i]);
299 EXPECT_NE(®ister_values[i], &clone_values[i]);
300 }
301 }
302
TEST_F(RegsTest,clone)303 TEST_F(RegsTest, clone) {
304 std::vector<std::unique_ptr<Regs>> regs;
305 regs.emplace_back(new RegsArm());
306 regs.emplace_back(new RegsArm64());
307 regs.emplace_back(new RegsX86());
308 regs.emplace_back(new RegsX86_64());
309 regs.emplace_back(new RegsMips());
310 regs.emplace_back(new RegsMips64());
311
312 for (auto& r : regs) {
313 if (r->Is32Bit()) {
314 clone_test<uint32_t>(r.get());
315 } else {
316 clone_test<uint64_t>(r.get());
317 }
318 }
319 }
320
321 } // namespace unwindstack
322