1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _SDE_DRM_H_ 20 #define _SDE_DRM_H_ 21 #define SDE_MAX_PLANES 4 22 #define SDE_MAX_DE_CURVES 3 23 #define FILTER_EDGE_DIRECTED_2D 0x0 24 #define FILTER_CIRCULAR_2D 0x1 25 #define FILTER_SEPARABLE_1D 0x2 26 #define FILTER_BILINEAR 0x3 27 #define FILTER_ALPHA_DROP_REPEAT 0x0 28 #define FILTER_ALPHA_BILINEAR 0x1 29 #define FILTER_ALPHA_2D 0x3 30 #define FILTER_BLEND_CIRCULAR_2D 0x0 31 #define FILTER_BLEND_SEPARABLE_1D 0x1 32 #define SCALER_LUT_SWAP 0x1 33 #define SCALER_LUT_DIR_WR 0x2 34 #define SCALER_LUT_Y_CIR_WR 0x4 35 #define SCALER_LUT_UV_CIR_WR 0x8 36 #define SCALER_LUT_Y_SEP_WR 0x10 37 #define SCALER_LUT_UV_SEP_WR 0x20 38 #define SDE_DRM_BLEND_OP_NOT_DEFINED 0 39 #define SDE_DRM_BLEND_OP_OPAQUE 1 40 #define SDE_DRM_BLEND_OP_PREMULTIPLIED 2 41 #define SDE_DRM_BLEND_OP_COVERAGE 3 42 #define SDE_DRM_BLEND_OP_MAX 4 43 #define SDE_DRM_DEINTERLACE 0 44 #define SDE_DRM_BITMASK_COUNT 64 45 struct sde_drm_pix_ext_v1 { 46 int32_t num_ext_pxls_lr[SDE_MAX_PLANES]; 47 int32_t num_ext_pxls_tb[SDE_MAX_PLANES]; 48 int32_t left_ftch[SDE_MAX_PLANES]; 49 int32_t right_ftch[SDE_MAX_PLANES]; 50 int32_t top_ftch[SDE_MAX_PLANES]; 51 int32_t btm_ftch[SDE_MAX_PLANES]; 52 int32_t left_rpt[SDE_MAX_PLANES]; 53 int32_t right_rpt[SDE_MAX_PLANES]; 54 int32_t top_rpt[SDE_MAX_PLANES]; 55 int32_t btm_rpt[SDE_MAX_PLANES]; 56 }; 57 #define SDE_DRM_SCALER_PIX_EXT 0x1 58 #define SDE_DRM_SCALER_SCALER_2 0x2 59 #define SDE_DRM_SCALER_SCALER_3 0x4 60 #define SDE_DRM_SCALER_DECIMATE 0x8 61 struct sde_drm_scaler_v1 { 62 uint32_t enable; 63 struct sde_drm_pix_ext_v1 pe; 64 uint32_t horz_decimate; 65 uint32_t vert_decimate; 66 int32_t init_phase_x[SDE_MAX_PLANES]; 67 int32_t phase_step_x[SDE_MAX_PLANES]; 68 int32_t init_phase_y[SDE_MAX_PLANES]; 69 int32_t phase_step_y[SDE_MAX_PLANES]; 70 uint32_t horz_filter[SDE_MAX_PLANES]; 71 uint32_t vert_filter[SDE_MAX_PLANES]; 72 }; 73 struct sde_drm_de_v1 { 74 uint32_t enable; 75 int16_t sharpen_level1; 76 int16_t sharpen_level2; 77 uint16_t clip; 78 uint16_t limit; 79 uint16_t thr_quiet; 80 uint16_t thr_dieout; 81 uint16_t thr_low; 82 uint16_t thr_high; 83 uint16_t prec_shift; 84 int16_t adjust_a[SDE_MAX_DE_CURVES]; 85 int16_t adjust_b[SDE_MAX_DE_CURVES]; 86 int16_t adjust_c[SDE_MAX_DE_CURVES]; 87 }; 88 struct sde_drm_scaler_v2 { 89 uint32_t enable; 90 uint32_t dir_en; 91 struct sde_drm_pix_ext_v1 pe; 92 uint32_t horz_decimate; 93 uint32_t vert_decimate; 94 int32_t init_phase_x[SDE_MAX_PLANES]; 95 int32_t phase_step_x[SDE_MAX_PLANES]; 96 int32_t init_phase_y[SDE_MAX_PLANES]; 97 int32_t phase_step_y[SDE_MAX_PLANES]; 98 uint32_t preload_x[SDE_MAX_PLANES]; 99 uint32_t preload_y[SDE_MAX_PLANES]; 100 uint32_t src_width[SDE_MAX_PLANES]; 101 uint32_t src_height[SDE_MAX_PLANES]; 102 uint32_t dst_width; 103 uint32_t dst_height; 104 uint32_t y_rgb_filter_cfg; 105 uint32_t uv_filter_cfg; 106 uint32_t alpha_filter_cfg; 107 uint32_t blend_cfg; 108 uint32_t lut_flag; 109 uint32_t dir_lut_idx; 110 uint32_t y_rgb_cir_lut_idx; 111 uint32_t uv_cir_lut_idx; 112 uint32_t y_rgb_sep_lut_idx; 113 uint32_t uv_sep_lut_idx; 114 struct sde_drm_de_v1 de; 115 }; 116 #define SDE_DRM_SCALER_V1 0x1 117 #define SDE_DRM_SCALER_VERSION SDE_DRM_SCALER_V1 118 struct sde_drm_scaler { 119 uint64_t version; 120 union { 121 struct sde_drm_scaler_v1 v1; 122 }; 123 }; 124 #define SDE_CSC_MATRIX_COEFF_SIZE 9 125 #define SDE_CSC_CLAMP_SIZE 6 126 #define SDE_CSC_BIAS_SIZE 3 127 #define SDE_DRM_CSC_V1 0x1 128 #define SDE_DRM_CSC_VERSION SDE_DRM_CSC_V1 129 struct sde_drm_csc_v1 { 130 int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE]; 131 uint32_t pre_bias[SDE_CSC_BIAS_SIZE]; 132 uint32_t post_bias[SDE_CSC_BIAS_SIZE]; 133 uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE]; 134 uint32_t post_clamp[SDE_CSC_CLAMP_SIZE]; 135 }; 136 struct sde_drm_csc { 137 uint64_t version; 138 union { 139 struct sde_drm_csc_v1 v1; 140 }; 141 }; 142 #define SDE_DRM_WB_CFG 0x1 143 #define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1 << 0) 144 struct sde_drm_wb_cfg { 145 uint32_t flags; 146 uint32_t connector_id; 147 uint32_t count_modes; 148 uint64_t modes; 149 }; 150 #endif 151 152