1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef HABANALABS_H_ 20 #define HABANALABS_H_ 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 24 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 27 enum goya_queue_id { 28 GOYA_QUEUE_ID_DMA_0 = 0, 29 GOYA_QUEUE_ID_DMA_1 = 1, 30 GOYA_QUEUE_ID_DMA_2 = 2, 31 GOYA_QUEUE_ID_DMA_3 = 3, 32 GOYA_QUEUE_ID_DMA_4 = 4, 33 GOYA_QUEUE_ID_CPU_PQ = 5, 34 GOYA_QUEUE_ID_MME = 6, 35 GOYA_QUEUE_ID_TPC0 = 7, 36 GOYA_QUEUE_ID_TPC1 = 8, 37 GOYA_QUEUE_ID_TPC2 = 9, 38 GOYA_QUEUE_ID_TPC3 = 10, 39 GOYA_QUEUE_ID_TPC4 = 11, 40 GOYA_QUEUE_ID_TPC5 = 12, 41 GOYA_QUEUE_ID_TPC6 = 13, 42 GOYA_QUEUE_ID_TPC7 = 14, 43 GOYA_QUEUE_ID_SIZE 44 }; 45 enum gaudi_queue_id { 46 GAUDI_QUEUE_ID_DMA_0_0 = 0, 47 GAUDI_QUEUE_ID_DMA_0_1 = 1, 48 GAUDI_QUEUE_ID_DMA_0_2 = 2, 49 GAUDI_QUEUE_ID_DMA_0_3 = 3, 50 GAUDI_QUEUE_ID_DMA_1_0 = 4, 51 GAUDI_QUEUE_ID_DMA_1_1 = 5, 52 GAUDI_QUEUE_ID_DMA_1_2 = 6, 53 GAUDI_QUEUE_ID_DMA_1_3 = 7, 54 GAUDI_QUEUE_ID_CPU_PQ = 8, 55 GAUDI_QUEUE_ID_DMA_2_0 = 9, 56 GAUDI_QUEUE_ID_DMA_2_1 = 10, 57 GAUDI_QUEUE_ID_DMA_2_2 = 11, 58 GAUDI_QUEUE_ID_DMA_2_3 = 12, 59 GAUDI_QUEUE_ID_DMA_3_0 = 13, 60 GAUDI_QUEUE_ID_DMA_3_1 = 14, 61 GAUDI_QUEUE_ID_DMA_3_2 = 15, 62 GAUDI_QUEUE_ID_DMA_3_3 = 16, 63 GAUDI_QUEUE_ID_DMA_4_0 = 17, 64 GAUDI_QUEUE_ID_DMA_4_1 = 18, 65 GAUDI_QUEUE_ID_DMA_4_2 = 19, 66 GAUDI_QUEUE_ID_DMA_4_3 = 20, 67 GAUDI_QUEUE_ID_DMA_5_0 = 21, 68 GAUDI_QUEUE_ID_DMA_5_1 = 22, 69 GAUDI_QUEUE_ID_DMA_5_2 = 23, 70 GAUDI_QUEUE_ID_DMA_5_3 = 24, 71 GAUDI_QUEUE_ID_DMA_6_0 = 25, 72 GAUDI_QUEUE_ID_DMA_6_1 = 26, 73 GAUDI_QUEUE_ID_DMA_6_2 = 27, 74 GAUDI_QUEUE_ID_DMA_6_3 = 28, 75 GAUDI_QUEUE_ID_DMA_7_0 = 29, 76 GAUDI_QUEUE_ID_DMA_7_1 = 30, 77 GAUDI_QUEUE_ID_DMA_7_2 = 31, 78 GAUDI_QUEUE_ID_DMA_7_3 = 32, 79 GAUDI_QUEUE_ID_MME_0_0 = 33, 80 GAUDI_QUEUE_ID_MME_0_1 = 34, 81 GAUDI_QUEUE_ID_MME_0_2 = 35, 82 GAUDI_QUEUE_ID_MME_0_3 = 36, 83 GAUDI_QUEUE_ID_MME_1_0 = 37, 84 GAUDI_QUEUE_ID_MME_1_1 = 38, 85 GAUDI_QUEUE_ID_MME_1_2 = 39, 86 GAUDI_QUEUE_ID_MME_1_3 = 40, 87 GAUDI_QUEUE_ID_TPC_0_0 = 41, 88 GAUDI_QUEUE_ID_TPC_0_1 = 42, 89 GAUDI_QUEUE_ID_TPC_0_2 = 43, 90 GAUDI_QUEUE_ID_TPC_0_3 = 44, 91 GAUDI_QUEUE_ID_TPC_1_0 = 45, 92 GAUDI_QUEUE_ID_TPC_1_1 = 46, 93 GAUDI_QUEUE_ID_TPC_1_2 = 47, 94 GAUDI_QUEUE_ID_TPC_1_3 = 48, 95 GAUDI_QUEUE_ID_TPC_2_0 = 49, 96 GAUDI_QUEUE_ID_TPC_2_1 = 50, 97 GAUDI_QUEUE_ID_TPC_2_2 = 51, 98 GAUDI_QUEUE_ID_TPC_2_3 = 52, 99 GAUDI_QUEUE_ID_TPC_3_0 = 53, 100 GAUDI_QUEUE_ID_TPC_3_1 = 54, 101 GAUDI_QUEUE_ID_TPC_3_2 = 55, 102 GAUDI_QUEUE_ID_TPC_3_3 = 56, 103 GAUDI_QUEUE_ID_TPC_4_0 = 57, 104 GAUDI_QUEUE_ID_TPC_4_1 = 58, 105 GAUDI_QUEUE_ID_TPC_4_2 = 59, 106 GAUDI_QUEUE_ID_TPC_4_3 = 60, 107 GAUDI_QUEUE_ID_TPC_5_0 = 61, 108 GAUDI_QUEUE_ID_TPC_5_1 = 62, 109 GAUDI_QUEUE_ID_TPC_5_2 = 63, 110 GAUDI_QUEUE_ID_TPC_5_3 = 64, 111 GAUDI_QUEUE_ID_TPC_6_0 = 65, 112 GAUDI_QUEUE_ID_TPC_6_1 = 66, 113 GAUDI_QUEUE_ID_TPC_6_2 = 67, 114 GAUDI_QUEUE_ID_TPC_6_3 = 68, 115 GAUDI_QUEUE_ID_TPC_7_0 = 69, 116 GAUDI_QUEUE_ID_TPC_7_1 = 70, 117 GAUDI_QUEUE_ID_TPC_7_2 = 71, 118 GAUDI_QUEUE_ID_TPC_7_3 = 72, 119 GAUDI_QUEUE_ID_NIC_0_0 = 73, 120 GAUDI_QUEUE_ID_NIC_0_1 = 74, 121 GAUDI_QUEUE_ID_NIC_0_2 = 75, 122 GAUDI_QUEUE_ID_NIC_0_3 = 76, 123 GAUDI_QUEUE_ID_NIC_1_0 = 77, 124 GAUDI_QUEUE_ID_NIC_1_1 = 78, 125 GAUDI_QUEUE_ID_NIC_1_2 = 79, 126 GAUDI_QUEUE_ID_NIC_1_3 = 80, 127 GAUDI_QUEUE_ID_NIC_2_0 = 81, 128 GAUDI_QUEUE_ID_NIC_2_1 = 82, 129 GAUDI_QUEUE_ID_NIC_2_2 = 83, 130 GAUDI_QUEUE_ID_NIC_2_3 = 84, 131 GAUDI_QUEUE_ID_NIC_3_0 = 85, 132 GAUDI_QUEUE_ID_NIC_3_1 = 86, 133 GAUDI_QUEUE_ID_NIC_3_2 = 87, 134 GAUDI_QUEUE_ID_NIC_3_3 = 88, 135 GAUDI_QUEUE_ID_NIC_4_0 = 89, 136 GAUDI_QUEUE_ID_NIC_4_1 = 90, 137 GAUDI_QUEUE_ID_NIC_4_2 = 91, 138 GAUDI_QUEUE_ID_NIC_4_3 = 92, 139 GAUDI_QUEUE_ID_NIC_5_0 = 93, 140 GAUDI_QUEUE_ID_NIC_5_1 = 94, 141 GAUDI_QUEUE_ID_NIC_5_2 = 95, 142 GAUDI_QUEUE_ID_NIC_5_3 = 96, 143 GAUDI_QUEUE_ID_NIC_6_0 = 97, 144 GAUDI_QUEUE_ID_NIC_6_1 = 98, 145 GAUDI_QUEUE_ID_NIC_6_2 = 99, 146 GAUDI_QUEUE_ID_NIC_6_3 = 100, 147 GAUDI_QUEUE_ID_NIC_7_0 = 101, 148 GAUDI_QUEUE_ID_NIC_7_1 = 102, 149 GAUDI_QUEUE_ID_NIC_7_2 = 103, 150 GAUDI_QUEUE_ID_NIC_7_3 = 104, 151 GAUDI_QUEUE_ID_NIC_8_0 = 105, 152 GAUDI_QUEUE_ID_NIC_8_1 = 106, 153 GAUDI_QUEUE_ID_NIC_8_2 = 107, 154 GAUDI_QUEUE_ID_NIC_8_3 = 108, 155 GAUDI_QUEUE_ID_NIC_9_0 = 109, 156 GAUDI_QUEUE_ID_NIC_9_1 = 110, 157 GAUDI_QUEUE_ID_NIC_9_2 = 111, 158 GAUDI_QUEUE_ID_NIC_9_3 = 112, 159 GAUDI_QUEUE_ID_SIZE 160 }; 161 enum goya_engine_id { 162 GOYA_ENGINE_ID_DMA_0 = 0, 163 GOYA_ENGINE_ID_DMA_1, 164 GOYA_ENGINE_ID_DMA_2, 165 GOYA_ENGINE_ID_DMA_3, 166 GOYA_ENGINE_ID_DMA_4, 167 GOYA_ENGINE_ID_MME_0, 168 GOYA_ENGINE_ID_TPC_0, 169 GOYA_ENGINE_ID_TPC_1, 170 GOYA_ENGINE_ID_TPC_2, 171 GOYA_ENGINE_ID_TPC_3, 172 GOYA_ENGINE_ID_TPC_4, 173 GOYA_ENGINE_ID_TPC_5, 174 GOYA_ENGINE_ID_TPC_6, 175 GOYA_ENGINE_ID_TPC_7, 176 GOYA_ENGINE_ID_SIZE 177 }; 178 enum gaudi_engine_id { 179 GAUDI_ENGINE_ID_DMA_0 = 0, 180 GAUDI_ENGINE_ID_DMA_1, 181 GAUDI_ENGINE_ID_DMA_2, 182 GAUDI_ENGINE_ID_DMA_3, 183 GAUDI_ENGINE_ID_DMA_4, 184 GAUDI_ENGINE_ID_DMA_5, 185 GAUDI_ENGINE_ID_DMA_6, 186 GAUDI_ENGINE_ID_DMA_7, 187 GAUDI_ENGINE_ID_MME_0, 188 GAUDI_ENGINE_ID_MME_1, 189 GAUDI_ENGINE_ID_MME_2, 190 GAUDI_ENGINE_ID_MME_3, 191 GAUDI_ENGINE_ID_TPC_0, 192 GAUDI_ENGINE_ID_TPC_1, 193 GAUDI_ENGINE_ID_TPC_2, 194 GAUDI_ENGINE_ID_TPC_3, 195 GAUDI_ENGINE_ID_TPC_4, 196 GAUDI_ENGINE_ID_TPC_5, 197 GAUDI_ENGINE_ID_TPC_6, 198 GAUDI_ENGINE_ID_TPC_7, 199 GAUDI_ENGINE_ID_NIC_0, 200 GAUDI_ENGINE_ID_NIC_1, 201 GAUDI_ENGINE_ID_NIC_2, 202 GAUDI_ENGINE_ID_NIC_3, 203 GAUDI_ENGINE_ID_NIC_4, 204 GAUDI_ENGINE_ID_NIC_5, 205 GAUDI_ENGINE_ID_NIC_6, 206 GAUDI_ENGINE_ID_NIC_7, 207 GAUDI_ENGINE_ID_NIC_8, 208 GAUDI_ENGINE_ID_NIC_9, 209 GAUDI_ENGINE_ID_SIZE 210 }; 211 enum hl_device_status { 212 HL_DEVICE_STATUS_OPERATIONAL, 213 HL_DEVICE_STATUS_IN_RESET, 214 HL_DEVICE_STATUS_MALFUNCTION, 215 HL_DEVICE_STATUS_NEEDS_RESET 216 }; 217 #define HL_INFO_HW_IP_INFO 0 218 #define HL_INFO_HW_EVENTS 1 219 #define HL_INFO_DRAM_USAGE 2 220 #define HL_INFO_HW_IDLE 3 221 #define HL_INFO_DEVICE_STATUS 4 222 #define HL_INFO_DEVICE_UTILIZATION 6 223 #define HL_INFO_HW_EVENTS_AGGREGATE 7 224 #define HL_INFO_CLK_RATE 8 225 #define HL_INFO_RESET_COUNT 9 226 #define HL_INFO_TIME_SYNC 10 227 #define HL_INFO_CS_COUNTERS 11 228 #define HL_INFO_PCI_COUNTERS 12 229 #define HL_INFO_CLK_THROTTLE_REASON 13 230 #define HL_INFO_SYNC_MANAGER 14 231 #define HL_INFO_TOTAL_ENERGY 15 232 #define HL_INFO_PLL_FREQUENCY 16 233 #define HL_INFO_VERSION_MAX_LEN 128 234 #define HL_INFO_CARD_NAME_MAX_LEN 16 235 struct hl_info_hw_ip_info { 236 __u64 sram_base_address; 237 __u64 dram_base_address; 238 __u64 dram_size; 239 __u32 sram_size; 240 __u32 num_of_events; 241 __u32 device_id; 242 __u32 module_id; 243 __u32 reserved; 244 __u16 first_available_interrupt_id; 245 __u16 reserved2; 246 __u32 cpld_version; 247 __u32 psoc_pci_pll_nr; 248 __u32 psoc_pci_pll_nf; 249 __u32 psoc_pci_pll_od; 250 __u32 psoc_pci_pll_div_factor; 251 __u8 tpc_enabled_mask; 252 __u8 dram_enabled; 253 __u8 pad[2]; 254 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 255 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 256 __u64 reserved3; 257 __u64 dram_page_size; 258 }; 259 struct hl_info_dram_usage { 260 __u64 dram_free_mem; 261 __u64 ctx_dram_mem; 262 }; 263 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2 264 struct hl_info_hw_idle { 265 __u32 is_idle; 266 __u32 busy_engines_mask; 267 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 268 }; 269 struct hl_info_device_status { 270 __u32 status; 271 __u32 pad; 272 }; 273 struct hl_info_device_utilization { 274 __u32 utilization; 275 __u32 pad; 276 }; 277 struct hl_info_clk_rate { 278 __u32 cur_clk_rate_mhz; 279 __u32 max_clk_rate_mhz; 280 }; 281 struct hl_info_reset_count { 282 __u32 hard_reset_cnt; 283 __u32 soft_reset_cnt; 284 }; 285 struct hl_info_time_sync { 286 __u64 device_time; 287 __u64 host_time; 288 }; 289 struct hl_info_pci_counters { 290 __u64 rx_throughput; 291 __u64 tx_throughput; 292 __u64 replay_cnt; 293 }; 294 #define HL_CLK_THROTTLE_POWER 0x1 295 #define HL_CLK_THROTTLE_THERMAL 0x2 296 struct hl_info_clk_throttle { 297 __u32 clk_throttling_reason; 298 }; 299 struct hl_info_energy { 300 __u64 total_energy_consumption; 301 }; 302 #define HL_PLL_NUM_OUTPUTS 4 303 struct hl_pll_frequency_info { 304 __u16 output[HL_PLL_NUM_OUTPUTS]; 305 }; 306 struct hl_info_sync_manager { 307 __u32 first_available_sync_object; 308 __u32 first_available_monitor; 309 __u32 first_available_cq; 310 __u32 reserved; 311 }; 312 struct hl_info_cs_counters { 313 __u64 total_out_of_mem_drop_cnt; 314 __u64 ctx_out_of_mem_drop_cnt; 315 __u64 total_parsing_drop_cnt; 316 __u64 ctx_parsing_drop_cnt; 317 __u64 total_queue_full_drop_cnt; 318 __u64 ctx_queue_full_drop_cnt; 319 __u64 total_device_in_reset_drop_cnt; 320 __u64 ctx_device_in_reset_drop_cnt; 321 __u64 total_max_cs_in_flight_drop_cnt; 322 __u64 ctx_max_cs_in_flight_drop_cnt; 323 __u64 total_validation_drop_cnt; 324 __u64 ctx_validation_drop_cnt; 325 }; 326 enum gaudi_dcores { 327 HL_GAUDI_WS_DCORE, 328 HL_GAUDI_WN_DCORE, 329 HL_GAUDI_EN_DCORE, 330 HL_GAUDI_ES_DCORE 331 }; 332 struct hl_info_args { 333 __u64 return_pointer; 334 __u32 return_size; 335 __u32 op; 336 union { 337 __u32 dcore_id; 338 __u32 ctx_id; 339 __u32 period_ms; 340 __u32 pll_index; 341 }; 342 __u32 pad; 343 }; 344 #define HL_CB_OP_CREATE 0 345 #define HL_CB_OP_DESTROY 1 346 #define HL_CB_OP_INFO 2 347 #define HL_MAX_CB_SIZE (0x200000 - 32) 348 #define HL_CB_FLAGS_MAP 0x1 349 struct hl_cb_in { 350 __u64 cb_handle; 351 __u32 op; 352 __u32 cb_size; 353 __u32 ctx_id; 354 __u32 flags; 355 }; 356 struct hl_cb_out { 357 union { 358 __u64 cb_handle; 359 struct { 360 __u32 usage_cnt; 361 __u32 pad; 362 }; 363 }; 364 }; 365 union hl_cb_args { 366 struct hl_cb_in in; 367 struct hl_cb_out out; 368 }; 369 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 370 struct hl_cs_chunk { 371 union { 372 __u64 cb_handle; 373 __u64 signal_seq_arr; 374 }; 375 __u32 queue_index; 376 union { 377 __u32 cb_size; 378 __u32 num_signal_seq_arr; 379 }; 380 __u32 cs_chunk_flags; 381 __u32 collective_engine_id; 382 __u32 pad[10]; 383 }; 384 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 385 #define HL_CS_FLAGS_SIGNAL 0x2 386 #define HL_CS_FLAGS_WAIT 0x4 387 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 388 #define HL_CS_FLAGS_TIMESTAMP 0x20 389 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 390 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 391 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 392 #define HL_CS_STATUS_SUCCESS 0 393 #define HL_MAX_JOBS_PER_CS 512 394 struct hl_cs_in { 395 __u64 chunks_restore; 396 __u64 chunks_execute; 397 union { 398 __u64 chunks_store; 399 __u64 seq; 400 }; 401 __u32 num_chunks_restore; 402 __u32 num_chunks_execute; 403 __u32 num_chunks_store; 404 __u32 cs_flags; 405 __u32 ctx_id; 406 }; 407 struct hl_cs_out { 408 __u64 seq; 409 __u32 status; 410 __u32 pad; 411 }; 412 union hl_cs_args { 413 struct hl_cs_in in; 414 struct hl_cs_out out; 415 }; 416 struct hl_wait_cs_in { 417 __u64 seq; 418 __u64 timeout_us; 419 __u32 ctx_id; 420 __u32 pad; 421 }; 422 #define HL_WAIT_CS_STATUS_COMPLETED 0 423 #define HL_WAIT_CS_STATUS_BUSY 1 424 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 425 #define HL_WAIT_CS_STATUS_ABORTED 3 426 #define HL_WAIT_CS_STATUS_INTERRUPTED 4 427 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 428 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 429 struct hl_wait_cs_out { 430 __u32 status; 431 __u32 flags; 432 __s64 timestamp_nsec; 433 }; 434 union hl_wait_cs_args { 435 struct hl_wait_cs_in in; 436 struct hl_wait_cs_out out; 437 }; 438 #define HL_MEM_OP_ALLOC 0 439 #define HL_MEM_OP_FREE 1 440 #define HL_MEM_OP_MAP 2 441 #define HL_MEM_OP_UNMAP 3 442 #define HL_MEM_OP_MAP_BLOCK 4 443 #define HL_MEM_CONTIGUOUS 0x1 444 #define HL_MEM_SHARED 0x2 445 #define HL_MEM_USERPTR 0x4 446 struct hl_mem_in { 447 union { 448 struct { 449 __u64 mem_size; 450 } alloc; 451 struct { 452 __u64 handle; 453 } free; 454 struct { 455 __u64 hint_addr; 456 __u64 handle; 457 } map_device; 458 struct { 459 __u64 host_virt_addr; 460 __u64 hint_addr; 461 __u64 mem_size; 462 } map_host; 463 struct { 464 __u64 block_addr; 465 } map_block; 466 struct { 467 __u64 device_virt_addr; 468 } unmap; 469 }; 470 __u32 op; 471 __u32 flags; 472 __u32 ctx_id; 473 __u32 pad; 474 }; 475 struct hl_mem_out { 476 union { 477 __u64 device_virt_addr; 478 __u64 handle; 479 struct { 480 __u64 block_handle; 481 __u32 block_size; 482 __u32 pad; 483 }; 484 }; 485 }; 486 union hl_mem_args { 487 struct hl_mem_in in; 488 struct hl_mem_out out; 489 }; 490 #define HL_DEBUG_MAX_AUX_VALUES 10 491 struct hl_debug_params_etr { 492 __u64 buffer_address; 493 __u64 buffer_size; 494 __u32 sink_mode; 495 __u32 pad; 496 }; 497 struct hl_debug_params_etf { 498 __u64 buffer_address; 499 __u64 buffer_size; 500 __u32 sink_mode; 501 __u32 pad; 502 }; 503 struct hl_debug_params_stm { 504 __u64 he_mask; 505 __u64 sp_mask; 506 __u32 id; 507 __u32 frequency; 508 }; 509 struct hl_debug_params_bmon { 510 __u64 start_addr0; 511 __u64 addr_mask0; 512 __u64 start_addr1; 513 __u64 addr_mask1; 514 __u32 bw_win; 515 __u32 win_capture; 516 __u32 id; 517 __u32 pad; 518 }; 519 struct hl_debug_params_spmu { 520 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 521 __u32 event_types_num; 522 __u32 pad; 523 }; 524 #define HL_DEBUG_OP_ETR 0 525 #define HL_DEBUG_OP_ETF 1 526 #define HL_DEBUG_OP_STM 2 527 #define HL_DEBUG_OP_FUNNEL 3 528 #define HL_DEBUG_OP_BMON 4 529 #define HL_DEBUG_OP_SPMU 5 530 #define HL_DEBUG_OP_TIMESTAMP 6 531 #define HL_DEBUG_OP_SET_MODE 7 532 struct hl_debug_args { 533 __u64 input_ptr; 534 __u64 output_ptr; 535 __u32 input_size; 536 __u32 output_size; 537 __u32 op; 538 __u32 reg_idx; 539 __u32 enable; 540 __u32 ctx_id; 541 }; 542 #define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args) 543 #define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args) 544 #define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args) 545 #define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args) 546 #define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args) 547 #define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args) 548 #define HL_COMMAND_START 0x01 549 #define HL_COMMAND_END 0x07 550 #endif 551