1 /****************************************************************************
2  ****************************************************************************
3  ***
4  ***   This header was automatically generated from a Linux kernel header
5  ***   of the same name, to make information necessary for userspace to
6  ***   call into the kernel available to libc.  It contains only constants,
7  ***   structures, and macros generated from the original header, and thus,
8  ***   contains no copyrightable information.
9  ***
10  ***   To edit the content of this header, modify the corresponding
11  ***   source file (e.g. under external/kernel-headers/original/) then
12  ***   run bionic/libc/kernel/tools/update_all.py
13  ***
14  ***   Any manual change here will be lost the next time this script will
15  ***   be run. You've been warned!
16  ***
17  ****************************************************************************
18  ****************************************************************************/
19 #ifndef VIRTGPU_DRM_H
20 #define VIRTGPU_DRM_H
21 #include "drm.h"
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 #define DRM_VIRTGPU_MAP 0x01
26 #define DRM_VIRTGPU_EXECBUFFER 0x02
27 #define DRM_VIRTGPU_GETPARAM 0x03
28 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04
29 #define DRM_VIRTGPU_RESOURCE_INFO 0x05
30 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
31 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
32 #define DRM_VIRTGPU_WAIT 0x08
33 #define DRM_VIRTGPU_GET_CAPS 0x09
34 #define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
35 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
36 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
37 #define VIRTGPU_EXECBUF_FLAGS (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | 0)
38 struct drm_virtgpu_map {
39   __u64 offset;
40   __u32 handle;
41   __u32 pad;
42 };
43 struct drm_virtgpu_execbuffer {
44   __u32 flags;
45   __u32 size;
46   __u64 command;
47   __u64 bo_handles;
48   __u32 num_bo_handles;
49   __s32 fence_fd;
50 };
51 #define VIRTGPU_PARAM_3D_FEATURES 1
52 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2
53 #define VIRTGPU_PARAM_RESOURCE_BLOB 3
54 #define VIRTGPU_PARAM_HOST_VISIBLE 4
55 #define VIRTGPU_PARAM_CROSS_DEVICE 5
56 struct drm_virtgpu_getparam {
57   __u64 param;
58   __u64 value;
59 };
60 struct drm_virtgpu_resource_create {
61   __u32 target;
62   __u32 format;
63   __u32 bind;
64   __u32 width;
65   __u32 height;
66   __u32 depth;
67   __u32 array_size;
68   __u32 last_level;
69   __u32 nr_samples;
70   __u32 flags;
71   __u32 bo_handle;
72   __u32 res_handle;
73   __u32 size;
74   __u32 stride;
75 };
76 struct drm_virtgpu_resource_info {
77   __u32 bo_handle;
78   __u32 res_handle;
79   __u32 size;
80   __u32 blob_mem;
81 };
82 struct drm_virtgpu_3d_box {
83   __u32 x;
84   __u32 y;
85   __u32 z;
86   __u32 w;
87   __u32 h;
88   __u32 d;
89 };
90 struct drm_virtgpu_3d_transfer_to_host {
91   __u32 bo_handle;
92   struct drm_virtgpu_3d_box box;
93   __u32 level;
94   __u32 offset;
95   __u32 stride;
96   __u32 layer_stride;
97 };
98 struct drm_virtgpu_3d_transfer_from_host {
99   __u32 bo_handle;
100   struct drm_virtgpu_3d_box box;
101   __u32 level;
102   __u32 offset;
103   __u32 stride;
104   __u32 layer_stride;
105 };
106 #define VIRTGPU_WAIT_NOWAIT 1
107 struct drm_virtgpu_3d_wait {
108   __u32 handle;
109   __u32 flags;
110 };
111 struct drm_virtgpu_get_caps {
112   __u32 cap_set_id;
113   __u32 cap_set_ver;
114   __u64 addr;
115   __u32 size;
116   __u32 pad;
117 };
118 struct drm_virtgpu_resource_create_blob {
119 #define VIRTGPU_BLOB_MEM_GUEST 0x0001
120 #define VIRTGPU_BLOB_MEM_HOST3D 0x0002
121 #define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
122 #define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
123 #define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
124 #define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
125   __u32 blob_mem;
126   __u32 blob_flags;
127   __u32 bo_handle;
128   __u32 res_handle;
129   __u64 size;
130   __u32 pad;
131   __u32 cmd_size;
132   __u64 cmd;
133   __u64 blob_id;
134 };
135 #define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
136 #define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
137 #define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
138 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)
139 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)
140 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)
141 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)
142 #define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
143 #define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
144 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob)
145 #ifdef __cplusplus
146 }
147 #endif
148 #endif
149