1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _USR_IDXD_H_ 20 #define _USR_IDXD_H_ 21 #include <stdint.h> 22 #define IDXD_OP_FLAG_FENCE 0x0001 23 #define IDXD_OP_FLAG_BOF 0x0002 24 #define IDXD_OP_FLAG_CRAV 0x0004 25 #define IDXD_OP_FLAG_RCR 0x0008 26 #define IDXD_OP_FLAG_RCI 0x0010 27 #define IDXD_OP_FLAG_CRSTS 0x0020 28 #define IDXD_OP_FLAG_CR 0x0080 29 #define IDXD_OP_FLAG_CC 0x0100 30 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 31 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 32 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 33 #define IDXD_OP_FLAG_CR_TCS 0x1000 34 #define IDXD_OP_FLAG_STORD 0x2000 35 #define IDXD_OP_FLAG_DRDBK 0x4000 36 #define IDXD_OP_FLAG_DSTS 0x8000 37 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 38 enum dsa_opcode { 39 DSA_OPCODE_NOOP = 0, 40 DSA_OPCODE_BATCH, 41 DSA_OPCODE_DRAIN, 42 DSA_OPCODE_MEMMOVE, 43 DSA_OPCODE_MEMFILL, 44 DSA_OPCODE_COMPARE, 45 DSA_OPCODE_COMPVAL, 46 DSA_OPCODE_CR_DELTA, 47 DSA_OPCODE_AP_DELTA, 48 DSA_OPCODE_DUALCAST, 49 DSA_OPCODE_CRCGEN = 0x10, 50 DSA_OPCODE_COPY_CRC, 51 DSA_OPCODE_DIF_CHECK, 52 DSA_OPCODE_DIF_INS, 53 DSA_OPCODE_DIF_STRP, 54 DSA_OPCODE_DIF_UPDT, 55 DSA_OPCODE_CFLUSH = 0x20, 56 }; 57 enum iax_opcode { 58 IAX_OPCODE_NOOP = 0, 59 IAX_OPCODE_DRAIN = 2, 60 IAX_OPCODE_MEMMOVE, 61 IAX_OPCODE_DECOMPRESS = 0x42, 62 IAX_OPCODE_COMPRESS, 63 }; 64 enum dsa_completion_status { 65 DSA_COMP_NONE = 0, 66 DSA_COMP_SUCCESS, 67 DSA_COMP_SUCCESS_PRED, 68 DSA_COMP_PAGE_FAULT_NOBOF, 69 DSA_COMP_PAGE_FAULT_IR, 70 DSA_COMP_BATCH_FAIL, 71 DSA_COMP_BATCH_PAGE_FAULT, 72 DSA_COMP_DR_OFFSET_NOINC, 73 DSA_COMP_DR_OFFSET_ERANGE, 74 DSA_COMP_DIF_ERR, 75 DSA_COMP_BAD_OPCODE = 0x10, 76 DSA_COMP_INVALID_FLAGS, 77 DSA_COMP_NOZERO_RESERVE, 78 DSA_COMP_XFER_ERANGE, 79 DSA_COMP_DESC_CNT_ERANGE, 80 DSA_COMP_DR_ERANGE, 81 DSA_COMP_OVERLAP_BUFFERS, 82 DSA_COMP_DCAST_ERR, 83 DSA_COMP_DESCLIST_ALIGN, 84 DSA_COMP_INT_HANDLE_INVAL, 85 DSA_COMP_CRA_XLAT, 86 DSA_COMP_CRA_ALIGN, 87 DSA_COMP_ADDR_ALIGN, 88 DSA_COMP_PRIV_BAD, 89 DSA_COMP_TRAFFIC_CLASS_CONF, 90 DSA_COMP_PFAULT_RDBA, 91 DSA_COMP_HW_ERR1, 92 DSA_COMP_HW_ERR_DRB, 93 DSA_COMP_TRANSLATION_FAIL, 94 }; 95 enum iax_completion_status { 96 IAX_COMP_NONE = 0, 97 IAX_COMP_SUCCESS, 98 IAX_COMP_PAGE_FAULT_IR = 0x04, 99 IAX_COMP_OUTBUF_OVERFLOW, 100 IAX_COMP_BAD_OPCODE = 0x10, 101 IAX_COMP_INVALID_FLAGS, 102 IAX_COMP_NOZERO_RESERVE, 103 IAX_COMP_INVALID_SIZE, 104 IAX_COMP_OVERLAP_BUFFERS = 0x16, 105 IAX_COMP_INT_HANDLE_INVAL = 0x19, 106 IAX_COMP_CRA_XLAT, 107 IAX_COMP_CRA_ALIGN, 108 IAX_COMP_ADDR_ALIGN, 109 IAX_COMP_PRIV_BAD, 110 IAX_COMP_TRAFFIC_CLASS_CONF, 111 IAX_COMP_PFAULT_RDBA, 112 IAX_COMP_HW_ERR1, 113 IAX_COMP_HW_ERR_DRB, 114 IAX_COMP_TRANSLATION_FAIL, 115 IAX_COMP_PRS_TIMEOUT, 116 IAX_COMP_WATCHDOG, 117 IAX_COMP_INVALID_COMP_FLAG = 0x30, 118 IAX_COMP_INVALID_FILTER_FLAG, 119 IAX_COMP_INVALID_NUM_ELEMS = 0x33, 120 }; 121 #define DSA_COMP_STATUS_MASK 0x7f 122 #define DSA_COMP_STATUS_WRITE 0x80 123 struct dsa_hw_desc { 124 uint32_t pasid : 20; 125 uint32_t rsvd : 11; 126 uint32_t priv : 1; 127 uint32_t flags : 24; 128 uint32_t opcode : 8; 129 uint64_t completion_addr; 130 union { 131 uint64_t src_addr; 132 uint64_t rdback_addr; 133 uint64_t pattern; 134 uint64_t desc_list_addr; 135 }; 136 union { 137 uint64_t dst_addr; 138 uint64_t rdback_addr2; 139 uint64_t src2_addr; 140 uint64_t comp_pattern; 141 }; 142 union { 143 uint32_t xfer_size; 144 uint32_t desc_count; 145 }; 146 uint16_t int_handle; 147 uint16_t rsvd1; 148 union { 149 uint8_t expected_res; 150 struct { 151 uint64_t delta_addr; 152 uint32_t max_delta_size; 153 uint32_t delt_rsvd; 154 uint8_t expected_res_mask; 155 }; 156 uint32_t delta_rec_size; 157 uint64_t dest2; 158 struct { 159 uint32_t crc_seed; 160 uint32_t crc_rsvd; 161 uint64_t seed_addr; 162 }; 163 struct { 164 uint8_t src_dif_flags; 165 uint8_t dif_chk_res; 166 uint8_t dif_chk_flags; 167 uint8_t dif_chk_res2[5]; 168 uint32_t chk_ref_tag_seed; 169 uint16_t chk_app_tag_mask; 170 uint16_t chk_app_tag_seed; 171 }; 172 struct { 173 uint8_t dif_ins_res; 174 uint8_t dest_dif_flag; 175 uint8_t dif_ins_flags; 176 uint8_t dif_ins_res2[13]; 177 uint32_t ins_ref_tag_seed; 178 uint16_t ins_app_tag_mask; 179 uint16_t ins_app_tag_seed; 180 }; 181 struct { 182 uint8_t src_upd_flags; 183 uint8_t upd_dest_flags; 184 uint8_t dif_upd_flags; 185 uint8_t dif_upd_res[5]; 186 uint32_t src_ref_tag_seed; 187 uint16_t src_app_tag_mask; 188 uint16_t src_app_tag_seed; 189 uint32_t dest_ref_tag_seed; 190 uint16_t dest_app_tag_mask; 191 uint16_t dest_app_tag_seed; 192 }; 193 uint8_t op_specific[24]; 194 }; 195 } __attribute__((packed)); 196 struct iax_hw_desc { 197 uint32_t pasid : 20; 198 uint32_t rsvd : 11; 199 uint32_t priv : 1; 200 uint32_t flags : 24; 201 uint32_t opcode : 8; 202 uint64_t completion_addr; 203 uint64_t src1_addr; 204 uint64_t dst_addr; 205 uint32_t src1_size; 206 uint16_t int_handle; 207 union { 208 uint16_t compr_flags; 209 uint16_t decompr_flags; 210 }; 211 uint64_t src2_addr; 212 uint32_t max_dst_size; 213 uint32_t src2_size; 214 uint32_t filter_flags; 215 uint32_t num_inputs; 216 } __attribute__((packed)); 217 struct dsa_raw_desc { 218 uint64_t field[8]; 219 } __attribute__((packed)); 220 struct dsa_completion_record { 221 volatile uint8_t status; 222 union { 223 uint8_t result; 224 uint8_t dif_status; 225 }; 226 uint16_t rsvd; 227 uint32_t bytes_completed; 228 uint64_t fault_addr; 229 union { 230 struct { 231 uint32_t invalid_flags : 24; 232 uint32_t rsvd2 : 8; 233 }; 234 uint32_t delta_rec_size; 235 uint32_t crc_val; 236 struct { 237 uint32_t dif_chk_ref_tag; 238 uint16_t dif_chk_app_tag_mask; 239 uint16_t dif_chk_app_tag; 240 }; 241 struct { 242 uint64_t dif_ins_res; 243 uint32_t dif_ins_ref_tag; 244 uint16_t dif_ins_app_tag_mask; 245 uint16_t dif_ins_app_tag; 246 }; 247 struct { 248 uint32_t dif_upd_src_ref_tag; 249 uint16_t dif_upd_src_app_tag_mask; 250 uint16_t dif_upd_src_app_tag; 251 uint32_t dif_upd_dest_ref_tag; 252 uint16_t dif_upd_dest_app_tag_mask; 253 uint16_t dif_upd_dest_app_tag; 254 }; 255 uint8_t op_specific[16]; 256 }; 257 } __attribute__((packed)); 258 struct dsa_raw_completion_record { 259 uint64_t field[4]; 260 } __attribute__((packed)); 261 struct iax_completion_record { 262 volatile uint8_t status; 263 uint8_t error_code; 264 uint16_t rsvd; 265 uint32_t bytes_completed; 266 uint64_t fault_addr; 267 uint32_t invalid_flags; 268 uint32_t rsvd2; 269 uint32_t output_size; 270 uint8_t output_bits; 271 uint8_t rsvd3; 272 uint16_t rsvd4; 273 uint64_t rsvd5[4]; 274 } __attribute__((packed)); 275 struct iax_raw_completion_record { 276 uint64_t field[8]; 277 } __attribute__((packed)); 278 #endif 279