1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef VIRTIO_GPU_HW_H 20 #define VIRTIO_GPU_HW_H 21 #include <linux/types.h> 22 #define VIRTIO_GPU_F_VIRGL 0 23 #define VIRTIO_GPU_F_EDID 1 24 #define VIRTIO_GPU_F_RESOURCE_UUID 2 25 #define VIRTIO_GPU_F_RESOURCE_BLOB 3 26 enum virtio_gpu_ctrl_type { 27 VIRTIO_GPU_UNDEFINED = 0, 28 VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100, 29 VIRTIO_GPU_CMD_RESOURCE_CREATE_2D, 30 VIRTIO_GPU_CMD_RESOURCE_UNREF, 31 VIRTIO_GPU_CMD_SET_SCANOUT, 32 VIRTIO_GPU_CMD_RESOURCE_FLUSH, 33 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D, 34 VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING, 35 VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING, 36 VIRTIO_GPU_CMD_GET_CAPSET_INFO, 37 VIRTIO_GPU_CMD_GET_CAPSET, 38 VIRTIO_GPU_CMD_GET_EDID, 39 VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID, 40 VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB, 41 VIRTIO_GPU_CMD_SET_SCANOUT_BLOB, 42 VIRTIO_GPU_CMD_CTX_CREATE = 0x0200, 43 VIRTIO_GPU_CMD_CTX_DESTROY, 44 VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, 45 VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE, 46 VIRTIO_GPU_CMD_RESOURCE_CREATE_3D, 47 VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, 48 VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D, 49 VIRTIO_GPU_CMD_SUBMIT_3D, 50 VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB, 51 VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB, 52 VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300, 53 VIRTIO_GPU_CMD_MOVE_CURSOR, 54 VIRTIO_GPU_RESP_OK_NODATA = 0x1100, 55 VIRTIO_GPU_RESP_OK_DISPLAY_INFO, 56 VIRTIO_GPU_RESP_OK_CAPSET_INFO, 57 VIRTIO_GPU_RESP_OK_CAPSET, 58 VIRTIO_GPU_RESP_OK_EDID, 59 VIRTIO_GPU_RESP_OK_RESOURCE_UUID, 60 VIRTIO_GPU_RESP_OK_MAP_INFO, 61 VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200, 62 VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY, 63 VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID, 64 VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID, 65 VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID, 66 VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER, 67 }; 68 enum virtio_gpu_shm_id { 69 VIRTIO_GPU_SHM_ID_UNDEFINED = 0, 70 VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1 71 }; 72 #define VIRTIO_GPU_FLAG_FENCE (1 << 0) 73 struct virtio_gpu_ctrl_hdr { 74 __le32 type; 75 __le32 flags; 76 __le64 fence_id; 77 __le32 ctx_id; 78 __le32 padding; 79 }; 80 struct virtio_gpu_cursor_pos { 81 __le32 scanout_id; 82 __le32 x; 83 __le32 y; 84 __le32 padding; 85 }; 86 struct virtio_gpu_update_cursor { 87 struct virtio_gpu_ctrl_hdr hdr; 88 struct virtio_gpu_cursor_pos pos; 89 __le32 resource_id; 90 __le32 hot_x; 91 __le32 hot_y; 92 __le32 padding; 93 }; 94 struct virtio_gpu_rect { 95 __le32 x; 96 __le32 y; 97 __le32 width; 98 __le32 height; 99 }; 100 struct virtio_gpu_resource_unref { 101 struct virtio_gpu_ctrl_hdr hdr; 102 __le32 resource_id; 103 __le32 padding; 104 }; 105 struct virtio_gpu_resource_create_2d { 106 struct virtio_gpu_ctrl_hdr hdr; 107 __le32 resource_id; 108 __le32 format; 109 __le32 width; 110 __le32 height; 111 }; 112 struct virtio_gpu_set_scanout { 113 struct virtio_gpu_ctrl_hdr hdr; 114 struct virtio_gpu_rect r; 115 __le32 scanout_id; 116 __le32 resource_id; 117 }; 118 struct virtio_gpu_resource_flush { 119 struct virtio_gpu_ctrl_hdr hdr; 120 struct virtio_gpu_rect r; 121 __le32 resource_id; 122 __le32 padding; 123 }; 124 struct virtio_gpu_transfer_to_host_2d { 125 struct virtio_gpu_ctrl_hdr hdr; 126 struct virtio_gpu_rect r; 127 __le64 offset; 128 __le32 resource_id; 129 __le32 padding; 130 }; 131 struct virtio_gpu_mem_entry { 132 __le64 addr; 133 __le32 length; 134 __le32 padding; 135 }; 136 struct virtio_gpu_resource_attach_backing { 137 struct virtio_gpu_ctrl_hdr hdr; 138 __le32 resource_id; 139 __le32 nr_entries; 140 }; 141 struct virtio_gpu_resource_detach_backing { 142 struct virtio_gpu_ctrl_hdr hdr; 143 __le32 resource_id; 144 __le32 padding; 145 }; 146 #define VIRTIO_GPU_MAX_SCANOUTS 16 147 struct virtio_gpu_resp_display_info { 148 struct virtio_gpu_ctrl_hdr hdr; 149 struct virtio_gpu_display_one { 150 struct virtio_gpu_rect r; 151 __le32 enabled; 152 __le32 flags; 153 } pmodes[VIRTIO_GPU_MAX_SCANOUTS]; 154 }; 155 struct virtio_gpu_box { 156 __le32 x, y, z; 157 __le32 w, h, d; 158 }; 159 struct virtio_gpu_transfer_host_3d { 160 struct virtio_gpu_ctrl_hdr hdr; 161 struct virtio_gpu_box box; 162 __le64 offset; 163 __le32 resource_id; 164 __le32 level; 165 __le32 stride; 166 __le32 layer_stride; 167 }; 168 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0) 169 struct virtio_gpu_resource_create_3d { 170 struct virtio_gpu_ctrl_hdr hdr; 171 __le32 resource_id; 172 __le32 target; 173 __le32 format; 174 __le32 bind; 175 __le32 width; 176 __le32 height; 177 __le32 depth; 178 __le32 array_size; 179 __le32 last_level; 180 __le32 nr_samples; 181 __le32 flags; 182 __le32 padding; 183 }; 184 struct virtio_gpu_ctx_create { 185 struct virtio_gpu_ctrl_hdr hdr; 186 __le32 nlen; 187 __le32 padding; 188 char debug_name[64]; 189 }; 190 struct virtio_gpu_ctx_destroy { 191 struct virtio_gpu_ctrl_hdr hdr; 192 }; 193 struct virtio_gpu_ctx_resource { 194 struct virtio_gpu_ctrl_hdr hdr; 195 __le32 resource_id; 196 __le32 padding; 197 }; 198 struct virtio_gpu_cmd_submit { 199 struct virtio_gpu_ctrl_hdr hdr; 200 __le32 size; 201 __le32 padding; 202 }; 203 #define VIRTIO_GPU_CAPSET_VIRGL 1 204 #define VIRTIO_GPU_CAPSET_VIRGL2 2 205 struct virtio_gpu_get_capset_info { 206 struct virtio_gpu_ctrl_hdr hdr; 207 __le32 capset_index; 208 __le32 padding; 209 }; 210 struct virtio_gpu_resp_capset_info { 211 struct virtio_gpu_ctrl_hdr hdr; 212 __le32 capset_id; 213 __le32 capset_max_version; 214 __le32 capset_max_size; 215 __le32 padding; 216 }; 217 struct virtio_gpu_get_capset { 218 struct virtio_gpu_ctrl_hdr hdr; 219 __le32 capset_id; 220 __le32 capset_version; 221 }; 222 struct virtio_gpu_resp_capset { 223 struct virtio_gpu_ctrl_hdr hdr; 224 __u8 capset_data[]; 225 }; 226 struct virtio_gpu_cmd_get_edid { 227 struct virtio_gpu_ctrl_hdr hdr; 228 __le32 scanout; 229 __le32 padding; 230 }; 231 struct virtio_gpu_resp_edid { 232 struct virtio_gpu_ctrl_hdr hdr; 233 __le32 size; 234 __le32 padding; 235 __u8 edid[1024]; 236 }; 237 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0) 238 struct virtio_gpu_config { 239 __le32 events_read; 240 __le32 events_clear; 241 __le32 num_scanouts; 242 __le32 num_capsets; 243 }; 244 enum virtio_gpu_formats { 245 VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM = 1, 246 VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM = 2, 247 VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM = 3, 248 VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM = 4, 249 VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM = 67, 250 VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM = 68, 251 VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM = 121, 252 VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM = 134, 253 }; 254 struct virtio_gpu_resource_assign_uuid { 255 struct virtio_gpu_ctrl_hdr hdr; 256 __le32 resource_id; 257 __le32 padding; 258 }; 259 struct virtio_gpu_resp_resource_uuid { 260 struct virtio_gpu_ctrl_hdr hdr; 261 __u8 uuid[16]; 262 }; 263 struct virtio_gpu_resource_create_blob { 264 struct virtio_gpu_ctrl_hdr hdr; 265 __le32 resource_id; 266 #define VIRTIO_GPU_BLOB_MEM_GUEST 0x0001 267 #define VIRTIO_GPU_BLOB_MEM_HOST3D 0x0002 268 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST 0x0003 269 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE 0x0001 270 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE 0x0002 271 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 272 __le32 blob_mem; 273 __le32 blob_flags; 274 __le32 nr_entries; 275 __le64 blob_id; 276 __le64 size; 277 }; 278 struct virtio_gpu_set_scanout_blob { 279 struct virtio_gpu_ctrl_hdr hdr; 280 struct virtio_gpu_rect r; 281 __le32 scanout_id; 282 __le32 resource_id; 283 __le32 width; 284 __le32 height; 285 __le32 format; 286 __le32 padding; 287 __le32 strides[4]; 288 __le32 offsets[4]; 289 }; 290 struct virtio_gpu_resource_map_blob { 291 struct virtio_gpu_ctrl_hdr hdr; 292 __le32 resource_id; 293 __le32 padding; 294 __le64 offset; 295 }; 296 #define VIRTIO_GPU_MAP_CACHE_MASK 0x0f 297 #define VIRTIO_GPU_MAP_CACHE_NONE 0x00 298 #define VIRTIO_GPU_MAP_CACHE_CACHED 0x01 299 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02 300 #define VIRTIO_GPU_MAP_CACHE_WC 0x03 301 struct virtio_gpu_resp_map_info { 302 struct virtio_gpu_ctrl_hdr hdr; 303 __u32 map_info; 304 __u32 padding; 305 }; 306 struct virtio_gpu_resource_unmap_blob { 307 struct virtio_gpu_ctrl_hdr hdr; 308 __le32 resource_id; 309 __le32 padding; 310 }; 311 #endif 312