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Searched refs:reg_w (Results 1 – 3 of 3) sorted by relevance

/aosp12/art/compiler/utils/arm64/
H A Djni_macro_assembler_arm64.cc36 #define reg_w(W) Arm64Assembler::reg_w(W) macro
114 ___ Str(reg_w(source), MEM_OP(reg_x(base), offset)); in StoreWToOffset()
229 ___ Ldr(reg_w(dest), MEM_OP(reg_x(base), offset)); in LoadWFromOffset()
306 asm_.MaybeUnpoisonHeapReference(reg_w(ref_reg)); in LoadRef()
431 ___ Mov(reg_w(dst.AsOverlappingWRegister()), reg_w(src.AsWRegister())); in Move()
441 ___ Mov(reg_w(dst.AsWRegister()), reg_w(src.AsWRegister())); in Move()
601 ___ Sxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in SignExtend()
603 ___ Sxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in SignExtend()
612 ___ Uxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in ZeroExtend()
614 ___ Uxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in ZeroExtend()
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H A Dmanaged_register_arm64_test.cc636 EXPECT_TRUE(vixl::aarch64::w0.Is(Arm64Assembler::reg_w(W0))); in TEST()
637 EXPECT_TRUE(vixl::aarch64::w1.Is(Arm64Assembler::reg_w(W1))); in TEST()
638 EXPECT_TRUE(vixl::aarch64::w2.Is(Arm64Assembler::reg_w(W2))); in TEST()
639 EXPECT_TRUE(vixl::aarch64::w3.Is(Arm64Assembler::reg_w(W3))); in TEST()
640 EXPECT_TRUE(vixl::aarch64::w4.Is(Arm64Assembler::reg_w(W4))); in TEST()
641 EXPECT_TRUE(vixl::aarch64::w5.Is(Arm64Assembler::reg_w(W5))); in TEST()
642 EXPECT_TRUE(vixl::aarch64::w6.Is(Arm64Assembler::reg_w(W6))); in TEST()
643 EXPECT_TRUE(vixl::aarch64::w7.Is(Arm64Assembler::reg_w(W7))); in TEST()
644 EXPECT_TRUE(vixl::aarch64::w8.Is(Arm64Assembler::reg_w(W8))); in TEST()
645 EXPECT_TRUE(vixl::aarch64::w9.Is(Arm64Assembler::reg_w(W9))); in TEST()
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H A Dassembler_arm64.h173 static vixl::aarch64::Register reg_w(int code) { in reg_w() function