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Searched refs:first_reg (Results 1 – 7 of 7) sorted by relevance

/aosp12/art/runtime/gc/space/
H A Dregion_space-inl.h410 Region* first_reg = &regions_[left]; in AllocLargeInRange() local
411 DCHECK(first_reg->IsFree()); in AllocLargeInRange()
412 first_reg->UnfreeLarge(this, time_); in AllocLargeInRange()
421 first_reg->SetTop(first_reg->Begin() + allocated); in AllocLargeInRange()
424 first_reg->SetNewlyAllocated(); in AllocLargeInRange()
445 mirror::Object* large_region = reinterpret_cast<mirror::Object*>(first_reg->Begin()); in AllocLargeInRange()
/aosp12/art/libdexfile/dex/
H A Ddex_instruction.cc402 uint16_t first_reg = VRegC_3rc(); in DumpString() local
412 os << StringPrintf("%s, {v%d .. v%d}, ", opcode, first_reg, last_reg) in DumpString()
420 os << StringPrintf("%s, {v%d .. v%d}, ", opcode, first_reg, last_reg) in DumpString()
426 os << StringPrintf("%s, {v%d .. v%d}, ", opcode, first_reg, last_reg) in DumpString()
/aosp12/bionic/libc/kernel/uapi/linux/
H A Dbcache.h191 __u32 first_reg; member
216 __u32 first_reg; member
/aosp12/art/compiler/optimizing/
H A Dcode_generator_x86_64.cc4580 __ shll(first_reg, second_reg); in HandleShift()
4589 __ shll(first_reg, imm); in HandleShift()
4591 __ sarl(first_reg, imm); in HandleShift()
4593 __ shrl(first_reg, imm); in HandleShift()
4611 __ shlq(first_reg, imm); in HandleShift()
4613 __ sarq(first_reg, imm); in HandleShift()
4615 __ shrq(first_reg, imm); in HandleShift()
4654 __ rorl(first_reg, second_reg); in VisitRor()
4657 __ rorl(first_reg, imm); in VisitRor()
4663 __ rorq(first_reg, second_reg); in VisitRor()
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H A Dinstruction_builder.h127 uint16_t first_reg,
H A Dcode_generator_arm_vixl.cc5243 __ Lsl(out_reg, first_reg, out_reg); in HandleShift()
5245 __ Asr(out_reg, first_reg, out_reg); in HandleShift()
5247 __ Lsr(out_reg, first_reg, out_reg); in HandleShift()
5253 __ Mov(out_reg, first_reg); in HandleShift()
5255 __ Lsl(out_reg, first_reg, shift_value); in HandleShift()
5257 __ Asr(out_reg, first_reg, shift_value); in HandleShift()
8447 __ Bic(out_reg, first_reg, second_reg); in VisitBitwiseNegatedRight()
8450 __ Orn(out_reg, first_reg, second_reg); in VisitBitwiseNegatedRight()
8697 __ And(out_reg, first_reg, second_reg); in HandleBitwiseOperation()
8699 __ Orr(out_reg, first_reg, second_reg); in HandleBitwiseOperation()
[all …]
H A Dcode_generator_x86.cc4612 Register first_reg = first.AsRegister<Register>(); in HandleShift() local
4617 __ shll(first_reg, second_reg); in HandleShift()
4619 __ sarl(first_reg, second_reg); in HandleShift()
4621 __ shrl(first_reg, second_reg); in HandleShift()
4630 __ shll(first_reg, imm); in HandleShift()
4632 __ sarl(first_reg, imm); in HandleShift()
4634 __ shrl(first_reg, imm); in HandleShift()
4804 Register first_reg = first.AsRegister<Register>(); in VisitRor() local
4807 __ rorl(first_reg, second_reg); in VisitRor()
4810 __ rorl(first_reg, imm); in VisitRor()