1 /* 2 * mipi_tx_hi35xx.h 3 * 4 * hi35xx mipi_tx driver implement. 5 * 6 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef MIPI_TX_HI35XX_H 20 #define MIPI_TX_HI35XX_H 21 22 /**************************************************************************** 23 * macro definition * 24 ****************************************************************************/ 25 #define MIPI_TX_REGS_ADDR 0x11270000 26 #define MIPI_TX_REGS_SIZE 0x10000 27 28 #define MIPI_TX_IRQ 120 29 30 #define MIPI_TX_CRG 0x1201010C 31 32 #define MIPI_TX_REF_CLK 27 33 34 #define TLPX 60 35 #define TCLK_PREPARE 60 36 #define TCLK_ZERO 250 37 #define TCLK_TRAIL 80 38 #define TPRE_DELAY 100 39 #define THS_PREPARE 80 40 #define THS_ZERO 180 41 #define THS_TRAIL 110 42 43 /* phy addr */ 44 #define PLL_SET0 0x60 45 #define PLL_SET1 0x64 46 #define PLL_SET2 0x65 47 #ifdef HI_FPGA 48 #define PLL_SET3 0x17 49 #endif 50 #define PLL_SET4 0x66 51 #define PLL_SET5 0x67 52 53 #define DATA0_TPRE_DELAY 0x28 54 #define DATA1_TPRE_DELAY 0x38 55 #define DATA2_TPRE_DELAY 0x48 56 #define DATA3_TPRE_DELAY 0x58 57 58 #define CLK_TLPX 0x10 59 #define CLK_TCLK_PREPARE 0x11 60 #define CLK_TCLK_ZERO 0x12 61 #define CLK_TCLK_TRAIL 0x13 62 63 #define DATA0_TLPX 0x20 64 #define DATA0_THS_PREPARE 0x21 65 #define DATA0_THS_ZERO 0x22 66 #define DATA0_THS_TRAIL 0x23 67 #define DATA1_TLPX 0x30 68 #define DATA1_THS_PREPARE 0x31 69 #define DATA1_THS_ZERO 0x32 70 #define DATA1_THS_TRAIL 0x33 71 #define DATA2_TLPX 0x40 72 #define DATA2_THS_PREPARE 0x41 73 #define DATA2_THS_ZERO 0x42 74 #define DATA2_THS_TRAIL 0x43 75 #define DATA3_TLPX 0x50 76 #define DATA3_THS_PREPARE 0x51 77 #define DATA3_THS_ZERO 0x52 78 #define DATA3_THS_TRAIL 0x53 79 80 #define MIPI_TX_READ_TIMEOUT_CNT 1000 81 82 #define PREPARE_COMPENSATE 10 83 #define ROUNDUP_VALUE 7999 84 #define INNER_PEROID 8000 /* 8 * 1000 ,1000 is 1us = 1000ns, 8 is division ratio */ 85 86 typedef struct { 87 unsigned char dataTpreDelay; 88 unsigned char clkTlpx; 89 unsigned char clkTclkPrepare; 90 unsigned char clkTclkZero; 91 unsigned char clkTclkTrail; 92 unsigned char dataTlpx; 93 unsigned char dataThsPrepare; 94 unsigned char dataThsZero; 95 unsigned char dataThsTrail; 96 } MipiTxPhyTimingParamTag; 97 98 typedef struct { 99 unsigned int vallDet; 100 unsigned int vactDet; 101 unsigned int hallDet; 102 unsigned int hactDet; 103 unsigned int hbpDet; 104 unsigned int hsaDet; 105 unsigned int vsaDet; 106 } MipiTxDevPhyTag; 107 108 void MipiTxDrvGetDevStatus(MipiTxDevPhyTag *phyCtx); 109 #endif /* MIPI_TX_HI35XX_H */ 110