Lines Matching refs:AddProperty
554 AddProperty(DRMProperty::MODE_ID, blob_id, true); in Perform()
561 AddProperty(DRMProperty::OUTPUT_FENCE_OFFSET, offset); in Perform()
566 AddProperty(DRMProperty::CORE_CLK, core_clk); in Perform()
571 AddProperty(DRMProperty::CORE_AB, core_ab); in Perform()
576 AddProperty(DRMProperty::CORE_IB, core_ib); in Perform()
581 AddProperty(DRMProperty::LLCC_AB, llcc_ab); in Perform()
586 AddProperty(DRMProperty::LLCC_IB, llcc_ib); in Perform()
591 AddProperty(DRMProperty::DRAM_AB, dram_ab); in Perform()
596 AddProperty(DRMProperty::DRAM_IB, dram_ib); in Perform()
601 AddProperty(DRMProperty::ROT_PREFILL_BW, rot_bw); in Perform()
606 AddProperty(DRMProperty::ROT_CLK, rot_clk); in Perform()
612 AddProperty(DRMProperty::OUTPUT_FENCE, in Perform()
618 AddProperty(DRMProperty::ACTIVE, enable); in Perform()
644 AddProperty(DRMProperty::SECURITY_LEVEL, crtc_security_level); in Perform()
656 AddProperty(DRMProperty::IDLE_TIME, timeout_ms); in Perform()
665 AddProperty(DRMProperty::DEST_SCALER, in Perform()
675 AddProperty(DRMProperty::CAPTURE_MODE, cwb_capture_mode); in Perform()
695 AddProperty(DRMProperty::IDLE_PC_STATE, idle_pc_state); in Perform()
711 AddProperty(DRMProperty::ROI_V1, 0, true); in SetROI()
727 AddProperty(DRMProperty::ROI_V1, reinterpret_cast<uint64_t>(&roi_v1_), true); in SetROI()
759 AddProperty(DRMProperty::DIM_STAGES_V1, in SetSolidfillStages()
775 AddProperty(DRMProperty::DS_LUT_ED, dir_lut_blob_id, true); in ConfigureScalerLUT()
778 AddProperty(DRMProperty::DS_LUT_CIR, cir_lut_blob_id, true); in ConfigureScalerLUT()
781 AddProperty(DRMProperty::DS_LUT_SEP, sep_lut_blob_id, true); in ConfigureScalerLUT()