Lines Matching refs:r12
83 .macro fetch, max_r=MAX_R, labelc=1, labelnc=2, reg=r12 /*{{{*/
84 .ifc \reg,r12 ; .set cc, 1 ; .else ; .set cc, 0 ; .endif
274 ldr r12, [pc, r5, LSL #2]
275 add pc, pc, r12
345 ldr r12, [pc, r5, LSL #2]
346 add pc, pc, r12
477 ldr r12, [pc, r5, LSL #2]
478 add pc, pc, r12
675 ldr r12, [pc, r5, LSL #2]
676 add pc, pc, r12
726 ldr r12, [pc, r5, LSL #2]
727 add pc, pc, r12
741 112: add r12, r9, #0x1a0
742 bic r12, r12, #0x200
743 vld1.u16 {d24,d25}, [r12:128]
748 111: add r12, r9, #0x1a8
749 bic r12, r12, #0x200
750 vld1.u16 {d24}, [r12:64]!
751 bic r12, r12, #0x200
752 vld1.u16 {d25}, [r12:64]
757 110: add r12, r9, #0x1b0
758 bic r12, r12, #0x200
759 vld1.u16 {d24,d25}, [r12:128]
764 109: add r12, r9, #0x1b8
765 bic r12, r12, #0x200
766 vld1.u16 {d24}, [r12:64]!
767 bic r12, r12, #0x200
768 vld1.u16 {d25}, [r12:64]
773 108: add r12, r9, #0x1c0
774 bic r12, r12, #0x200
775 vld1.u16 {d24,d25}, [r12:128]
780 107: add r12, r9, #0x1c8
781 bic r12, r12, #0x200
782 vld1.u16 {d24}, [r12:64]!
783 bic r12, r12, #0x200
784 vld1.u16 {d25}, [r12:64]
789 106: add r12, r9, #0x1d0
790 bic r12, r12, #0x200
791 vld1.u16 {d24,d25}, [r12:128]
796 105: add r12, r9, #0x1d8
797 bic r12, r12, #0x200
798 vld1.u16 {d24}, [r12:64]!
799 bic r12, r12, #0x200
800 vld1.u16 {d25}, [r12:64]
805 104: add r12, r9, #0x1e0
806 bic r12, r12, #0x200
807 vld1.u16 {d24,d25}, [r12:128]
812 103: add r12, r9, #0x1e8
813 bic r12, r12, #0x200
814 vld1.u16 {d24}, [r12:64]!
815 bic r12, r12, #0x200
816 vld1.u16 {d25}, [r12:64]
821 102: add r12, r9, #0x1f0
822 bic r12, r12, #0x200
823 vld1.u16 {d24,d25}, [r12:128]
828 101: add r12, r9, #0x1f8
829 bic r12, r12, #0x200
830 vld1.u16 {d24}, [r12:64]
852 add r12, r9, #0x198
853 bic r12, r12, #0x200
854 vld1.u16 {d24}, [r12:64]!
855 bic r12, r12, #0x200
856 vld1.u16 {d25}, [r12:64]
860 ldr r12, [pc, r5, LSL #2]
861 add pc, pc, r12
888 125: add r12, r9, #0x0d0
889 bic r12, r12, #0x200
890 vld1.u16 {d24,d25}, [r12:128]
895 124: add r12, r9, #0x0d8
896 bic r12, r12, #0x200
897 vld1.u16 {d24}, [r12:64]!
898 bic r12, r12, #0x200
899 vld1.u16 {d25}, [r12]
904 123: add r12, r9, #0x0e0
905 bic r12, r12, #0x200
906 vld1.u16 {d24,d25}, [r12:128]
911 122: add r12, r9, #0x0e8
912 bic r12, r12, #0x200
913 vld1.u16 {d24}, [r12:64]!
914 bic r12, r12, #0x200
915 vld1.u16 {d25}, [r12]
920 121: add r12, r9, #0x0f0
921 bic r12, r12, #0x200
922 vld1.u16 {d24,d25}, [r12:128]
927 120: add r12, r9, #0x0f8
928 bic r12, r12, #0x200
929 vld1.u16 {d24}, [r12:64]!
930 bic r12, r12, #0x200
931 vld1.u16 {d25}, [r12]
936 119: add r12, r9, #0x100
937 bic r12, r12, #0x200
938 vld1.u16 {d24,d25}, [r12:128]
943 118: add r12, r9, #0x108
944 bic r12, r12, #0x200
945 vld1.u16 {d24}, [r12:64]!
946 bic r12, r12, #0x200
947 vld1.u16 {d25}, [r12]
952 117: add r12, r9, #0x110
953 bic r12, r12, #0x200
954 vld1.u16 {d24,d25}, [r12:128]
959 116: add r12, r9, #0x118
960 bic r12, r12, #0x200
961 vld1.u16 {d24}, [r12:64]!
962 bic r12, r12, #0x200
963 vld1.u16 {d25}, [r12]
968 115: add r12, r9, #0x120
969 bic r12, r12, #0x200
970 vld1.u16 {d24,d25}, [r12:128]
975 114: add r12, r9, #0x128
976 bic r12, r12, #0x200
977 vld1.u16 {d24}, [r12:64]!
978 bic r12, r12, #0x200
979 vld1.u16 {d25}, [r12]
984 113: add r12, r9, #0x130
985 bic r12, r12, #0x200
986 vld1.u16 {d24,d25}, [r12:128]
991 112: add r12, r9, #0x138
992 bic r12, r12, #0x200
993 vld1.u16 {d24}, [r12:64]!
994 bic r12, r12, #0x200
995 vld1.u16 {d25}, [r12]
996 add r12, r9, #0x1f8
997 bic r12, r12, #0x200
998 vld1.u16 {d26}, [r12:64]
1003 111: add r12, r9, #0x140
1004 bic r12, r12, #0x200
1005 vld1.u16 {d24,d25}, [r12:128]
1006 add r12, r9, #0x1f0
1007 bic r12, r12, #0x200
1008 vld1.u16 {d26,d27}, [r12:128]
1013 110: add r12, r9, #0x148
1014 bic r12, r12, #0x200
1015 vld1.u16 {d24}, [r12:64]!
1016 bic r12, r12, #0x200
1017 vld1.u16 {d25}, [r12]
1018 add r12, r9, #0x1e8
1019 bic r12, r12, #0x200
1020 vld1.u16 {d26}, [r12:64]!
1021 bic r12, r12, #0x200
1022 vld1.u16 {d27}, [r12:64]
1027 109: add r12, r9, #0x150
1028 bic r12, r12, #0x200
1029 vld1.u16 {d24,d25}, [r12:128]
1030 add r12, r9, #0x1e0
1031 bic r12, r12, #0x200
1032 vld1.u16 {d26,d27}, [r12:128]
1037 108: add r12, r9, #0x158
1038 bic r12, r12, #0x200
1039 vld1.u16 {d24}, [r12:64]!
1040 bic r12, r12, #0x200
1041 vld1.u16 {d25}, [r12]
1042 add r12, r9, #0x1d8
1043 bic r12, r12, #0x200
1044 vld1.u16 {d26}, [r12:64]!
1045 bic r12, r12, #0x200
1046 vld1.u16 {d27}, [r12:64]
1051 107: add r12, r9, #0x160
1052 bic r12, r12, #0x200
1053 vld1.u16 {d24,d25}, [r12:128]
1054 add r12, r9, #0x1d0
1055 bic r12, r12, #0x200
1056 vld1.u16 {d26,d27}, [r12:128]
1061 106: add r12, r9, #0x168
1062 bic r12, r12, #0x200
1063 vld1.u16 {d24}, [r12:64]!
1064 bic r12, r12, #0x200
1065 vld1.u16 {d25}, [r12]
1066 add r12, r9, #0x1c8
1067 bic r12, r12, #0x200
1068 vld1.u16 {d26}, [r12:64]!
1069 bic r12, r12, #0x200
1070 vld1.u16 {d27}, [r12:64]
1075 105: add r12, r9, #0x170
1076 bic r12, r12, #0x200
1077 vld1.u16 {d24,d25}, [r12:128]
1078 add r12, r9, #0x1c0
1079 bic r12, r12, #0x200
1080 vld1.u16 {d26,d27}, [r12:128]
1085 104: add r12, r9, #0x178
1086 bic r12, r12, #0x200
1087 vld1.u16 {d24}, [r12:64]!
1088 bic r12, r12, #0x200
1089 vld1.u16 {d25}, [r12]
1090 add r12, r9, #0x1b8
1091 bic r12, r12, #0x200
1092 vld1.u16 {d26}, [r12:64]!
1093 bic r12, r12, #0x200
1094 vld1.u16 {d27}, [r12:64]
1099 103: add r12, r9, #0x180
1100 bic r12, r12, #0x200
1101 vld1.u16 {d24,d25}, [r12:128]
1102 add r12, r9, #0x1b0
1103 bic r12, r12, #0x200
1104 vld1.u16 {d26,d27}, [r12:128]
1109 102: add r12, r9, #0x188
1110 bic r12, r12, #0x200
1111 vld1.u16 {d24}, [r12:64]!
1112 bic r12, r12, #0x200
1113 vld1.u16 {d25}, [r12]
1114 add r12, r9, #0x1a8
1115 bic r12, r12, #0x200
1116 vld1.u16 {d26}, [r12:64]!
1117 bic r12, r12, #0x200
1118 vld1.u16 {d27}, [r12:64]
1123 101: add r12, r9, #0x190
1124 bic r12, r12, #0x200
1125 vld1.u16 {d24,d25}, [r12:128]!
1126 bic r12, r12, #0x200
1127 vld1.u16 {d26,d27}, [r12:128]
1167 push {r12,lr}
1171 ands r12, r10, #15
1173 sub r1, r1, r12
1174 sub r10, r10, r12
1177 sub r12, sp, r12, LSL #1
1180 vld1.u16 {q10,q11}, [r12]
1182 1: pop {r12,pc}
1186 push {r12,lr}
1192 ands r12, r10, #15
1194 sub r1, r1, r12
1195 sub r10, r10, r12
1198 sub r12, sp, r12, LSL #1
1201 vld1.u16 {q10,q11}, [r12]
1203 1: pop {r12,pc}
1214 push {r12, lr}
1215 rsb r12, r11, #0
1216 ands r12, r12, #15
1218 sub r1, r1, r12
1222 rsb r12, r11, #0
1223 and r12, r12, #15
1227 add r12, sp, r12, LSL #1
1229 vld1.u16 {q10,q11}, [r12]
1231 pop {r12,pc}
1235 pop {r12,pc}
1239 push {r12, lr}
1240 rsb r12, r11, #0
1241 ands r12, r12, #15
1243 sub r1, r1, r12
1249 rsb r12, r11, #0
1250 and r12, r12, #15
1254 add r12, sp, r12, LSL #1
1256 vld1.u16 {q10,q11}, [r12]
1258 pop {r12,pc}
1264 pop {r12,pc}
1276 ands r12, r11, #15
1278 sub r12, r12, #1
1281 add r12, sp, r12, LSL #1
1282 vld1.u16 {d24[],d25[]}, [r12]
1283 vld1.u16 {d26[],d27[]}, [r12]
1284 vst1.u16 {q12,q13}, [r12]
1294 ands r12, r11, #15
1296 sub r12, r12, #4
1299 add r12, sp, r12, LSL #1
1300 vld1.u64 {d24}, [r12]
1301 vld1.u64 {d25}, [r12]
1302 vld1.u64 {d26}, [r12]
1303 vld1.u64 {d27}, [r12]
1304 vst1.u16 {q12,q13}, [r12]
1534 sub r12, r11, #1
1535 eor r12, r10, r12
1536 cmp r12, #16
1583 add r12, r3, #15
1584 bic r12, r12, #15
1585 cmp r4, r12
1586 movhi r4, r12
1699 push {r12,lr}
1705 pop {r12,pc}
1711 push {r12,lr}
1726 pop {r12,pc}
1743 push {r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
1754 ldr r12, [sp,#124]
1763 vld1.u16 {d0,d1,d2,d3}, [r12]!
1764 vld1.u16 {d4,d5,d6}, [r12]!
1774 pop {r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}
1790 push {r4,r5,r6,r7,r8,r9,r10,r11,r12,lr}
1803 ldr r12, [sp,#124]
1812 vld1.u16 {d0,d1,d2,d3}, [r12]!
1813 vld1.u16 {d4,d5,d6}, [r12]!
1823 pop {r4,r5,r6,r7,r8,r9,r10,r11,r12,pc}