723   arm::CodeGeneratorARMVIXL codegen(graph, *compiler_options);  in TEST_F()  local
725   codegen.Initialize();  in TEST_F()
734   codegen.GetMoveResolver()->EmitNativeCode(move);  in TEST_F()
737   codegen.Finalize(&code_allocator);  in TEST_F()
747   arm64::CodeGeneratorARM64 codegen(graph, *compiler_options);  in TEST_F()  local
749   codegen.Initialize();  in TEST_F()
786   codegen.GetMoveResolver()->EmitNativeCode(move);  in TEST_F()
789   codegen.Finalize(&code_allocator);  in TEST_F()
797   arm64::CodeGeneratorARM64 codegen(graph, *compiler_options);  in TEST_F()  local
799   codegen.Initialize();  in TEST_F()
820     codegen.GetMoveResolver()->EmitNativeCode(move);  in TEST_F()
825   codegen.Finalize(&code_allocator);  in TEST_F()
833   arm64::CodeGeneratorARM64 codegen(graph, *compiler_options);  in TEST_F()  local
834   vixl::CPUFeatures* features = codegen.GetVIXLAssembler()->GetCPUFeatures();  in TEST_F()
848   arm64::CodeGeneratorARM64 codegen(graph, *compiler_options);  in TEST_F()  local
849   vixl::CPUFeatures* features = codegen.GetVIXLAssembler()->GetCPUFeatures();  in TEST_F()
867   arm64::CodeGeneratorARM64 codegen(graph, *compiler_options);  in TEST_F()  local
869   codegen.Initialize();  in TEST_F()
876     codegen.AddAllocatedRegister(Location::FpuRegisterLocation(reg_code));  in TEST_F()
878   codegen.ComputeSpillMask();  in TEST_F()
880   EXPECT_EQ(codegen.GetFpuSpillSize(), kExpectedFPSpillSize);  in TEST_F()
887   arm64::CodeGeneratorARM64 codegen(graph, *compiler_options);  in TEST_F()  local
889   codegen.Initialize();  in TEST_F()
896     codegen.AddAllocatedRegister(Location::FpuRegisterLocation(reg_code));  in TEST_F()
898   codegen.ComputeSpillMask();  in TEST_F()
900   EXPECT_EQ(codegen.GetFpuSpillSize(), kExpectedFPSpillSize);  in TEST_F()