Lines Matching refs:IsStackSlot

1623     } else if (source.IsStackSlot()) {  in Move()
1650 } else if (source.IsStackSlot()) { in Move()
1656 } else if (destination.IsStackSlot()) { in Move()
1668 DCHECK(source.IsStackSlot()) << source; in Move()
1802 DCHECK(right.IsStackSlot()); in GenerateCompareTest()
2185 } else if (rhs.IsStackSlot()) { in HandleCondition()
2359 } else if (right.IsStackSlot()) { in VisitCompare()
2794 if (receiver.IsStackSlot()) { in VisitInvokeInterface()
3086 } else if (in.IsStackSlot() || in.IsDoubleStackSlot()) { in VisitTypeConversion()
3110 } else if (in.IsStackSlot() || in.IsDoubleStackSlot()) { in VisitTypeConversion()
3133 } else if (in.IsStackSlot() || in.IsDoubleStackSlot()) { in VisitTypeConversion()
3155 } else if (in.IsStackSlot() || in.IsDoubleStackSlot()) { in VisitTypeConversion()
3503 DCHECK(second.IsStackSlot()); in VisitAdd()
3594 DCHECK(second.IsStackSlot()); in VisitSub()
3678 DCHECK(second.IsStackSlot()); in VisitMul()
3717 DCHECK(second.IsStackSlot()); in VisitMul()
3747 if (source.IsStackSlot()) { in PushOntoFPStack()
4179 DCHECK(second.IsStackSlot()); in VisitDiv()
4517 } else if (value.IsStackSlot()) { in VisitDivZeroCheck()
4734 if (location.IsStackSlot()) { in VisitParameterValue()
5334 } else if (obj.IsStackSlot()) { in GenerateExplicitNullCheck()
5946 } else if (destination.IsStackSlot()) { in EmitMove()
5954 } else if (source.IsStackSlot()) { in EmitMove()
5962 DCHECK(destination.IsStackSlot()); in EmitMove()
6001 DCHECK(destination.IsStackSlot()) << destination; in EmitMove()
6018 DCHECK(destination.IsStackSlot()) << destination; in EmitMove()
6037 } else if (destination.IsStackSlot()) { in EmitMove()
6130 } else if (source.IsRegister() && destination.IsStackSlot()) { in EmitSwap()
6132 } else if (source.IsStackSlot() && destination.IsRegister()) { in EmitSwap()
6134 } else if (source.IsStackSlot() && destination.IsStackSlot()) { in EmitSwap()
6146 } else if (source.IsFpuRegister() && destination.IsStackSlot()) { in EmitSwap()
6148 } else if (source.IsStackSlot() && destination.IsFpuRegister()) { in EmitSwap()
6666 DCHECK(cls.IsStackSlot()) << cls; in VisitInstanceOf()
6707 DCHECK(cls.IsStackSlot()) << cls; in VisitInstanceOf()
6733 DCHECK(cls.IsStackSlot()) << cls; in VisitInstanceOf()
6769 DCHECK(cls.IsStackSlot()) << cls; in VisitInstanceOf()
6802 DCHECK(cls.IsStackSlot()) << cls; in VisitInstanceOf()
6952 DCHECK(cls.IsStackSlot()) << cls; in VisitCheckCast()
6987 DCHECK(cls.IsStackSlot()) << cls; in VisitCheckCast()
7007 DCHECK(cls.IsStackSlot()) << cls; in VisitCheckCast()
7040 DCHECK(cls.IsStackSlot()) << cls; in VisitCheckCast()
7803 } else if (rhs.IsStackSlot()) { in GenerateIntCompare()